signal processing technologies, inc. 4755 forge road, colorado springs, colorado 80907, usa phone: (719) 528-2300 fax: (719) 528-2370 website: http://www.spt.com e-mail: sales@spt.com spt7862 10-bit, 40 msps, dual-channel a/d converter features ? dual-channel, 10-bit, 40 msps analog-to-digital converter ? low power dissipation: 320 mw (typical) ? internal track-and-hold ? single +5 volt supply ? tri-state, ttl/cmos-compatible outputs ? selectable +3 or +5 v logic i/o ? high esd protection of 3,500 volts minimum applications ? video set-top boxes ? cellular base stations ? qpsk/qam rf demodulation ? s-video digitizers ? composite video digitizers ? portable and handheld instrumentation ? medical ultrasound ? cable modems ? video frame grabbers general description the spt7862 contains two separate 10-bit cmos analog- to-digital converters that have sampling rates of up to 40 msps. each device has its own separate clock and refer- ence inputs so that they can be used independently in multichannel applications or can be driven from the same inputs for demanding quadrature demodulation and s-video applications. on-chip track-and-hold and advanced propri- etary circuit design in a cmos process technology provide very good dynamic performance. the spt7862 operates from a single +5 v supply. digital data outputs are user selectable at +3 or +5 v. output data format is straight binary. the spt7862 is available in a 64-lead tqfp package (10 x 10 mm) over the industrial temperature range of C40 c to +85 c. adc reference ladder timing generation v ina v rhfa v rhsa v rlfa v rlsa clk a adc reference ladder timing generation v inb v rhfb v rhsb v rlfb v rlsb clk b output buffers ov dda (+3.3/5.0 v) da9C0 en output buffers ov ddb (+3.3/5.0 v) db9C0 av dd agnd dv dd dgnd v inra v inrb ognd a ognd b dav b dav a block diagram
spt 2 2/23/00 spt7862 electrical specifications t a =t min to t max , av dd =dv dd =ov dd =+5.0 v, v in =0 to 4 v, ? s =40 msps, v rhs =4.0 v, v rls =0.0 v, unless otherwise specified. test test spt7862 parameters conditions level min typ max units resolution 10 bits dc accuracy integral nonlinearity v 1.0 lsb differential nonlinearity v 0.5 lsb analog input input voltage range iv v rls v rhs v input resistance v 29 k w input capacitance v 5.0 pf input bandwidth (small signal) v 250 mhz offset v 2.0 lsb gain error v 2.0 lsb reference input resistance v 500 w voltage range v rls iv 0 C 2.0 v v rhs iv 3.0 C av dd v v rhs C v rls v 1.0 4.0 5.0 v d (v rhf C v rhs )v90mv d (v rls C v rlf )v75mv conversion characteristics maximum conversion rate vi 40 mhz minimum conversion rate iv 2 mhz pipeline delay (latency) iv 12 clock cycles aperture delay time v 4.0 ns aperture jitter time v 7 ps(rms) dynamic performance effective number of bits ? in = 3.58 mhz v 9.1 bits ? in = 10.0 mhz vi 7.8 8.3 bits signal-to-noise ratio (without harmonics) ? in = 3.58 mhz v 57.9 db ? in = 10.0 mhz t a = +25 c i 52 54.2 db ? in = 10.0 mhz t a = t min to t max iv 47 db absolute maximum ratings (beyond which damage may occur) 1 25 c note: 1. operation at any absolute maximum rating is not implied. see electrical specifications for proper nominal applied conditions in typical applications. supply voltages av dd ......................................................................... +6 v dv dd ......................................................................... +6 v input voltages analog input ................................. C0.5 v to av dd +0.5 v v ref ................................................................. 0 to av dd clk input ................................................................... v dd av dd C dv dd ...................................................... 100 mv agnd C dgnd .................................................. 100 mv output digital outputs ....................................................... 10 ma temperature operating temperature ............................. C40 to +85 c junction temperature ......................................... +175 c lead temperature, (soldering 10 seconds) ........ +300 c storage temperature ............................... C65 to +150 c
spt 3 2/23/00 spt7862 dynamic performance harmonic distortion 9 distortion bins from ? in = 3.58 mhz 1024 pt fft v C63 db ? in = 10.0 mhz t a = +25 c i C55.7 C52 db ? in = 10.0 mhz t a = t min to t max iv C52 db signal-to-noise and distortion (sinad) ? in = 3.58 mhz v 56.7 db ? in = 10.0 mhz t a = +25 c i 49 51.8 db ? in = 10.0 mhz t a = t min to t max iv 46 db spurious free dynamic range ? in = 10.0 mhz v 56.8 58.3 60 db differential phase v 0.3 degree differential gain v 0.3 % channel-to-channel crosstalk ? in = 3.58 mhz v 74 db ? in = 10.0 mhz v 67 db inputs logic 1 voltage vi 2.1 v logic 0 voltage vi 0.8 v maximum input current low vi C10 +10 m a maximum input current high vi C10 +10 m a input capacitance v +5 pf digital outputs logic 1 voltage i oh = 0.5 ma vi ov dd C0.5 v logic 0 voltage i ol = 1.6 ma vi 0.44 v t rise 15 pf load v 10 ns t fall 15 pf load v 10 ns output enable to data output delay 20 pf load, t a = +25 c v 10 ns 50 pf load over temp. v 22 ns power supply requirements voltages ov dd iv 3.0 5.0 v dv dd iv 5.0 v av dd iv 5.0 v currents ai dd + di dd vi 52 62 ma oi dd vi 12 14 ma power dissipation vi 320 380 mw power supply refection ratio v 70 db test level codes all electrical characteristics are subject to the follow- ing conditions: all parameters having min/max specifications are guaranteed. the test level column indicates the specific device testing actually performed during production and quality assurance inspection. any blank section in the data column indicates that the specification is not tested at the specified condition. test procedure 100% production tested at the specified temperature. 100% production tested at t a =25 c, and sample tested at the specified temperatures. qa sample tested only at the specified temperatures. parameter is guaranteed (but not tested) by design and characterization data. parameter is a typical value for information purposes only. 100% production tested at t a = 25 c. parameter is guaran- teed over specified temperature range. test level i ii iii iv v vi electrical specifications t a =t min to t max , av dd =dv dd =ov dd =+5.0 v, v in =0 to 4 v, ? s =40 msps, v rhs =4.0 v, v rls =0.0 v, unless otherwise specified. test test spt7862 parameters conditions level min typ max units
spt 4 2/23/00 spt7862 table i C timing parameters figure 1a C timing diagram 1 t cl t ch data ? data 1 data 2 data 3 clock in data output data valid t s t s t od t ch t cl t c t clk description parameters min typ max units conversion time t c t clk ns clock period t clk 25 ns clock high duty cycle t ch 40 50 60 % clock low duty cycle t cl 40 50 60 % clock to output delay (30 pf load) t od 17 20 ns clock to dav (30 pf load) t s 10 16 ns analog in clock in 1 3 5 7 9 11 13 15 17 sampling clock (internal) data output data valid valid invalid 13 245 2 4 6 8 10 12 14 16 figure 1b C timing diagram 2
spt 5 2/23/00 spt7862 typical performance characteristics 65 60 55 50 45 40 70 0 5 10 15 20 thd snr sinad thd, snr, sinad vs input frequency input frequency (mhz) thd, snr, sinad (db) 0 10 30 50 thd snr sinad thd, snr, sinad vs sample rate sample rate (msps) thd, snr, sinad (db) 52040 1 65 60 55 50 45 40 70 ? in = 10 mhz 70 65 60 55 C55 C40 0 25 70 85 125 thd snr sinad thd, snr, sinad vs temperature temperature ( c) thd, snr, sinad (db) 50 45 40 C25 ? in = 10 mhz 0 10 30 50 power dissipation vs sample rate sample rate (msps) power dissipation (mw) 52040 1 500 400 300 200 100 0 600 60 ? in = 10 mhz spectral response frequency (mhz) amplitude (db)
spt 6 2/23/00 spt7862 typical interface circuit very few external components are required to achieve the stated device performance. figure 2 shows the typical inter- face requirements when using the spt7862 in normal circuit operation. the following sections provide descrip- tions of the major functions and outline critical performance criteria to consider for achieving the optimal device performance. power supplies and grounding spt suggests that both the digital and the analog supply voltages on the spt7862 be derived from a single analog supply as shown in figure 2. a separate digital supply should be used for all interface circuitry. spt suggests using this power supply configuration to prevent a possible latch-up condition on power up. operating description the general architecture for the dual cmos adc is shown in the block diagram. each adc design contains 16 identi- cal successive approximation (sar) adc sections (all oper- ating in parallel), a 16-phase clock generator, an 11-bit 16:1 digital output multiplexer, correction logic, and a voltage ref- erence generator which provides common reference levels for each adc section. the high sample rate is achieved by using multiple sar adc sections in parallel, each of which samples the input signal in sequence. each sar adc uses 16 clock cycles to complete a conversion. the clock cycles are allocated as follows: table ii C clock cycles clock operation 1 reference zero sampling 2 auto-zero comparison 3 auto-calibrate comparison 4 input sample 5C15 11-bit sar conversion 16 data transfer the 16-phase clock, which is derived from the input clock, synchronizes these events. the timing signals for adjacent sar adc sections are shifted by one clock cycle so that the analog input is sampled on every cycle of the input clock by exactly one sar adc section. after 16 clock periods, the timing cycle repeats. the latency from analog input sample to the corresponding digital output is 12 clock cycles. dv dd ov dda interface logic +d5v +a5 + +a5 + 10 m f +d5 interface logic +d5v +3v/5v +3v/5v 10 10 da9C0 ognd a dav a ov ddb db9C0 ognd b dav b en enable/tri-state (enable = active low) av dd fb clk b clock inb +5v analog +5v analog return v rhfa v rhsa v rlsa v rlfa v ina v inra v cal clk a v rhfb v rhsb v rlsb v rlfb v inb v inrb v ina clock ina ref in (+4v) agnd dgnd* spt7862 *to reduce the possibility of latch-up, avoid connecting the dgnd pins of the adc to the digital ground of the system. notes: 1. fb is a 10 m h inductor or ferrite bead. it is to be located as close to the device as possible. 2. all capacitors are 0.1 m f surface-mount, unless otherwise specified. ref in (+4v) +5v digital +5v digital return 10 m f v inb figure 2 C typical interface circuit
spt 7 2/23/00 spt7862 ? since only 16 comparators are used, a huge power sav- ings is realized. ? the auto-zero operation is done using a closed loop sys- tem that uses multiple samples of the comparators response to a reference zero. ? the auto-calibrate operation, which calibrates the gain of the msb reference and the lsb reference, is also done with a closed loop system. multiple samples of the gain error are inte grated to produce a calibration volt- age for each sar adc section. ? capacitive displacement currents, which can induce sam- pling error, are minimized since only one comparator samples the input during a clock cycle. ? the total input capacitance is very low, since sections of the converter which are not sampling the signal are iso- lated from the input by transmission gates. voltage reference the spt7862 requires the use of a single external voltage reference for driving the high side of each reference ladder. each ladder is totally independent and may operate at dif- ferent voltage levels. the high side of the reference ladder must operate within a range of 3 v to 5 v. the lower side of each ladder is typically tied to agnd (0.0 v), but can be run up to 2.0 v with a second reference. the analog input volt- age range will track the total voltage difference measured between the ladder sense lines, v rhs and v rls . force and sense taps are provided to ensure accurate and stable setting of the upper and lower ladder sense line volt- ages across part-to-part and temperature variations. by using the configuration shown in figure 3, offset and gain errors of less than 2 lsb can be obtained. in cases in which wider variations in offset and gain can be tolerated, the external reference can be tied directly to v rhf and agnd can be tied directly to v rlf as shown in figure 4. decouple force and sense lines to agnd with a .01 m f ca- pacitor (chip cap preferred) to minimize high-frequency noise injection. if this simplified configuration is used, the following considerations should be taken into account: the reference ladder circuit shown in figure 4 is a simplified representation of the actual reference ladder with force and sense taps shown. due to the actual internal structure of the ladder, the voltage drop from v rhf to v rhs is not equivalent to the voltage drop from v rlf to v rls . figure 3 C ladder force/sense circuit for each adc agnd v rhf v rhs v rls v rlf v in 1 2 3 5 6 7 + - + - all capacitors are 0.01 f 4 n/c figure 4 C simplified reference ladder drive circuit without force/sense circuit r/2 r r r r r r r/2 r=30 w (typ) all capacitors are 0.01 f v rlf (agnd) 0.0 v v rls (0.075 v) v rhs (+3.91 v) 90 mv 75 mv +4.0 v external reference typically, the top side voltage drop for v rhf to v rhs will equal: v rhf C v rhs = 2.25 % of (v rhf C v rlf ) (typical), and the bottom side voltage drop for v rls to v rlf will equal: v rls C v rlf = 1.9 % of (v rhf C v rlf ) (typical). figure 4 shows an example of expected voltage drops for a specific case. v ref of 4.0 v is applied to v rhf and v rlf is tied to agnd. a 90 mv drop is seen at v rhs (= 3.91 v) and a 75 mv increase is seen at v rls (= 0.075 v).
spt 8 2/23/00 spt7862 analog input v ina and v inb are the analog inputs and v inra and v inrb are the respective input returns. each input return is typically tied to its respective low side reference ladder sense line. (see figure 2.) the input voltage range is from v rls to v rhs (typically 4.0 v) and will scale proportionally with respect to the voltage reference. (see the voltage reference section.) the drive requirements for the analog inputs are very mini- mal, when compared to most other converters, due to the spt7862s extremely low input capacitance of only 5 pf and a high input resistance in excess of 29 k w . each analog input should be protected through a series resistor and diode clamping circuit as shown in figure 5. figure 6 C on-chip protection circuit v dd analog pad 120 w 120 w clock input each adc is driven independently from a single-ended ttl-input clock. because the pipelined architecture oper- ates on the rising edge of the clock input, each adc can operate over a wide range of input clock duty cycles without degrading the dynamic performance. digital outputs the digital outputs (da9C0 and db9C0) are driven by sepa- rate supplies (ov dda and ov ddb ) ranging from +3 v to +5 v. this feature makes it possible to drive the spt7862s ttl/cmos-compatible outputs with the users logic system supply. each digital output supply may be driven indepen- dently. the format of the output data (d0Cd9) is straight binary. (see table iii.) the outputs are latched on the rising edge of clk. the en pin controls tri-stating of both data output ports. these outputs can be switched into a tri-state mode by bringing en high. table iii C output data information analog input overrange output code d10 d9Cd0 +f.s. + 1/2 lsb 1 11 1111 1111 +f.s. C1/2 lsb 0 11 1111 111? +1/2 f.s. 0 ?? ???? ???? +1/2 lsb 0 00 0000 000? 0.0 v 0 00 0000 0000 (? indicates the flickering bit between logic 0 and 1) evaluation board the eb7862 evaluation board is available to aid designers in demonstrating the full performance of the spt7862. this board includes a reference circuit, clock driver circuit, output data latches and an on-board reconstruction of the digital data. an application note describing the operation of this board as well as information on the testing of the spt7862 is also available. contact the factory for price and availability. figure 5 C recommended input protection circuit 47 w d1 d2 adc buffer av dd +v Cv d1 = d2 = hewlett packard hp5712 or equivalent calibration the spt7862 uses a user-transparent, auto-calibration scheme to ensure 10-bit accuracy over time and tempera- ture. gain and offset errors are continually adjusted to 10-bit accuracy during device operation. upon power up, the spt7862 begins its calibration algo- rithm. in order to achieve the calibration accuracy required, the offset and gain adjustment step size is a fraction of a 10- bit lsb. since the calibration algorithm is an oversampling process, a minimum of 10,000 clock cycles are required. this results in a minimum calibration time upon power up of 250 m sec (for a 40 mhz clock). once calibrated, the spt7862 remains calibrated over time and temperature. since the calibration cycles are initiated on the rising edge of the clock, the clock must be continuously applied for the spt7862 to remain in calibration. input protection all i/o pads are protected with an on-chip protection circuit shown in figure 6. this circuit provides esd robustness and prevents latch-up under severe discharge conditions with- out degrading analog transition times.
spt 9 2/23/00 spt7862 inches millimeters symbol min max min max a 0.465 0.480 11.80 12.20 b 0.390 0.398 9.90 10.10 c 0.017 0.023 0.42 0.58 d 0.006 0.010 0.15 0.26 e 0.295 typ 7.5 typ f 0.433 typ 0.000 11 typ g 0.055 0.067 1.40 1.70 h 0.005 0.005 0.125 0.132 i 0-10 0-10 j 0.012 0.028 0.30 0.70 k 0.000 0.008 0.00 0.20 package outline 64-lead tqfp a b 64 49 1 48 33 32 17 16 c d e f g h i j k index
spt 10 2/23/00 spt7862 part number temperature range package type SPT7862SIT C40 to +85 c 64-lead tqfp ordering information signal processing technologies, inc. reserves the right to change products and specifications without notice. permission is her eby expressly granted to copy this literature for informational purposes only. copying this material for any other use is strictly prohibited . covered by patent numbers 5262779 and 5272481. warning C life support applications policy C spt products should not be used within life support systems without the specific written consent of spt. a life support system is a product or system intended to support or sustain life which, if it fails, ca n be reasonably expected to result in significant personal injury or death. signal processing technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. it is therefore not recommended, and exposure of a device to such a process will void the product warranty. pin assignments pin functions pin name description v ina analog input (a) v inb analog input (b) v inra analog input return (a) v inrb analog input return (b) v rhfa/b v ref high force input a/b v rhsa/b v ref high sense input a/b v rlfa/b v ref low force input a/b v rlsa/b v ref low sense input a/b av dd analog v dd dv dd digital v dd ov dd a/b digital output power supply +3.3 v to +5.0 v agnd analog ground dgnd digital ground ognd a/b digital output ground clk a/b input clock a/b (separate) en enable outputs (active low) d0C9a data outputs a (10 bits) d0C9b data outputs b (10 bits) dav a/b data available a/b v cal decoupling pin 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 db0 n/c ov ddb ognd b en dav b dgnd clkb n/c clka dv dd dav a ognd a ov dda n/c da0 v inrb v rlsa v rlsb v rlfa v rlfb n/c agnd v inb agnd v ina agnd v cal n/c agnd agnd n/c v inra v rhsb v rhsa v rhfb v rhfa agnd agnd db9 db8 db7 db6 db5 db4 db3 db2 db1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 agnd agnd n/c av dd av dd agnd agnd da9 da8 da7 da6 da5 da4 da3 da2 da1 spt7862 top view 64l tqfp
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